The present invention relates to an erasable nonvolatile semiconductor memory device such as an EPROM device, an EEPROM device, or a flash memory device. More particularly, it relates to a method for fabricating a nonvolatile semiconductor memory device having a logic circuit portion, including a peripheral circuit and the like, merged therein.
A description will be given herein below to a conventional method for fabricating a nonvolatile semiconductor memory device with reference to the drawings.
FIGS. 9A, 9B, 9C, 10A, 10B, 10C, 11A, and 11B show cross-sectional structures of a nonvolatile semiconductor memory device in the individual process steps of the conventional fabrication method therefor.
First, as shown in FIG. 9A, dielectric isolation films 102 are formed in a semiconductor substrate 101 made of P-type silicon and having a memory circuit portion 1B and a logic circuit portion 2B composing a peripheral circuit for the memory circuit portion 1B. Then, a protective insulating film 103 with a thickness of about 20 nm is formed over the entire surface of the semiconductor substrate 101.
Subsequently, a first resist pattern 201 having an opening corresponding to the memory circuit portion 1B of the semiconductor substrate 101 and to the region of the logic circuit portion 2B of the semiconductor substrate 101 to be formed with an N-type MOS transistor is formed on the protective insulating film 103. By using the first resist pattern 201 as a mask, boron ions are implanted into the semiconductor substrate 101 so that a first P-well 104 is formed.
Next, as shown in FIG. 9B, a second resist pattern 202 having an opening corresponding to the N-type MOS transistor formation region of the logic circuit portion 2B is formed on the protective insulating film 103. By using the second resist pattern 202 as a mask, boron ions are implanted for threshold voltage control so that a second P-well 105 is formed in the N-type MOS transistor formation region of the logic circuit portion 2B. Thus, the second P-well 105 is formed by two steps of boron ion implantation.
Next, as shown in FIG. 9C, a third resist pattern 203 having an opening corresponding to the region of the logic circuit portion 2B to be formed with a P-type MOS transistor is formed on the protective insulating film 103. By using the third resist pattern 203 as a mask, phosphorus ions are implanted into the semiconductor substrate 101 so that an N-well 106 is formed in the P-type MOS transistor formation region of the logic circuit portion 2B.
Next, as shown in FIG. 10A, the protective insulating film 103 is removed. Then, a first insulating film 107 with a thickness of about 10 nm, a first polysilicon film 108, and a second insulating film 109 composed of a multilayer structure of a silicon dioxide and a silicon nitride are grown successively on the semiconductor substrate 101.
Next, as shown in FIG. 10B, a fourth resist pattern 204 having an opening corresponding to the logic circuit portion 2B is formed on the second insulating film 109. By using the fourth resist pattern 204 as a mask, etching is performed sequentially with respect to the second insulating film 109, the first polysilicon film 108, and the first insulating film 107, thereby exposing the logic circuit portion 1B of the semiconductor substrate 101.
Next, as shown in FIG. 10C, the fourth resist pattern 204 is removed. Then, a third insulating film 110 and a second polysilicon film 111 are grown successively over the second insulating film 109 in the memory circuit portion 1B and the semiconductor substrate 101 in the logic circuit portion 2B.
Next, as shown in FIG. 11A, a fifth resist pattern 205 including a pattern for forming a gate electrode structure in the memory circuit portion 1B is formed on the second polysilicon film 111. By using the fifth resist pattern 205, the films grown successively on the semiconductor substrate 101 are patterned into the gate electrode structure. Specifically, a tunnel insulating film 107a is formed from the first insulating film 107, a floating fate 108a is formed from the first polysilicon film 108, a capacitance insulating film 112 is formed from the second and third insulating films 109 and 110, and a control gate 111a is formed from the second polysilicon film 111.
Next, as shown in FIG. 11B, the fifth resist pattern 205 is removed. Then, a sixth resist pattern 206 including a pattern for forming a gate electrode in the logic circuit portion 2B is formed on the second polysilicon film 111 covering the logic circuit portion 2B. By using the sixth resist pattern 206 as a mask, etching is performed sequentially with respect to the second polysilicon film 111 and the third insulating film 110, thereby forming a gate electrode 111b from the second polysilicon film 111 and forming a gate insulating film 110b from the third insulating film 110.
Thus, the conventional method for fabricating a nonvolatile semiconductor memory device has performed the implantation of boron ions into the N-type MOS transistor formation region of the logic circuit portion 2B simultaneously with the formation of the first P-well 104. Then, a thermal oxidation process at a temperature of about 850xc2x0 C. to 950xc2x0 C. is normally performed during the formation of the first insulating film 107 for forming the tunnel insulating film 107a shown in FIG. 10A. The formation of the first polysilicon film 111 for forming the floating gate 108a employs a low-pressure CVD process which requires a heating temperature of about 600xc2x0 C. to 700xc2x0 C.
Due to the thermal budget, an impurity concentration profile is diffused in the first P-well 104, in the second P-well 105, and in the N-well 106 so that the problems of a degraded dielectric isolation property and an increased drain-junction capacitance occur. In particular, a MOS transistor contained in the logic circuit portion 2B is required to have an excellent dielectric isolation property and a high drain-junction breakdown voltage so that it is seriously affected by the diffused impurity concentration profile in the wells 104, 105, and 106. If the MOS transistor is required to be further miniaturized, influence not only on the dielectric isolation property but also on a short-channel effect cannot be ignored.
As recent CMOS fabrication processes have been performed at lower temperatures, ion implantation with a high acceleration energy has been used more frequently to form each of the wells 105 and 106. If such ion implantation with a high acceleration energy is performed, a contaminant containing heavy metal and the like are likely to enter the semiconductor substrate 101 so that the problem of the degraded gate insulating film 110B also occurs.
To prevent the contaminant from entering the semiconductor substrate 101, the protective insulating film 103 is formed normally on the surface of the semiconductor substrate 101, as shown in FIG. 9A. However, the protective insulating film 103 has its upper portion graded during the removal of each of the resist patterns 201, 202, and 203 and the thickness thereof is gradually reduced. Consequently, the protective insulating film 103 cannot sufficiently perform the function of protecting the semiconductor substrate 101. These problems are increasingly aggravated as elements are further miniaturized to an extent that they cannot be cancelled out any more merely by reducing the number of process steps and cost.
It is therefore a first object of the present invention to solve the foregoing conventional problems and prevent, in a semiconductor device having a memory circuit portion and a logic circuit portion merged therein, a thermal budget resulting from process steps for fabricating the memory circuit portion from affecting the well regions of the logic circuit portion. A second object of the present invention is to prevent a contaminant from entering a substrate during ion implantation for forming the well regions.
To attain the first object, the present invention provides a method for forming a nonvolatile semiconductor device, the method comprising: a first step of selectively forming a first well region of a first conductivity type in a memory circuit portion of a semiconductor substrate having the memory circuit portion and a logic circuit portion; a second step of successively forming a first insulating film and a first conductor film over the memory circuit portion and the logic circuit portion of the semiconductor substrate; a third step of patterning the first insulating film and the first conductor film so as to leave respective regions of the first insulating film and the first conductor film contained in the memory circuit portion; a fourth step of selectively forming a second well region of the first conductivity type in the logic circuit portion of the semiconductor substrate; a fifth step of successively forming a second insulating film and a second conductor film over the first conductor film in the memory circuit portion and the second well region in the logic circuit portion; a sixth step of successively patterning the second conductor film, the second insulating film, the first conductor film, and the first insulating film contained in the memory circuit portion to form a control gate electrode from the second conductor film, form a capacitance insulating film from the second insulating film, form a floating gate electrode from the first conductor film, and form a tunnel insulating film from the first insulating film; and a seventh step of patterning respective regions of the second conductor film and the second insulating film contained in the logic circuit portion to form a gate electrode from the second conductor film and form a gate insulating film from the second insulating film.
In accordance with the method for fabricating a nonvolatile semiconductor memory device of the present invention, the second well region of the first conductivity type is formed in the logic circuit portion of the semiconductor substrate after the first insulating film for forming the tunnel insulating film and the first conductor film for forming the floating gate electrode are patterned. Consequently, the second well region in the logic circuit portion does not experience the thermal budget resulting from the formation of the first insulating film and the first conductor film. This prevents the degradation of a dielectric isolating property and an increase in drain-junction capacitance.
In the method for fabricating a nonvolatile semiconductor device of the present invention, the third step preferably includes etching a region of the first insulating film contained in the logic circuit portion such that a lower portion thereof is left to cover the logic circuit portion and thereby forming a partial film composed of the first insulating film and the fourth step preferably includes implanting ions into the logic circuit portion through the partial film. The second object is also achievable with the arrangement. Since the ion implantation is performed with respect to the logic circuit portion through the partial film composed of a lower portion of the first insulating film contained in the logic circuit portion during the formation of the second well region in the logic circuit portion, the entrance of a contaminant composed of heavy metal and the like into the semiconductor substrate due to an increased acceleration energy can be prevented.
Preferably, the method for fabricating a nonvolatile semiconductor device of the present invention further comprises, prior to the first step, the step of forming a protective insulating film over the entire surface of the semiconductor substrate, wherein the first step preferably includes forming the first well region by implanting ions through the protective insulating film and removing a region of the protective insulating film contained in the memory circuit portion, the second step preferably includes forming the first insulating film on the protective insulating film, the third step preferably includes performing the patterning so as to leave a region of the protective insulating film contained in the logic circuit portion, and the fourth step preferably includes implanting ions into the logic circuit portion through the protective insulating film.
The second object is also achievable with the arrangement. Since the ion implantation is performed with respect to the logic circuit portion with the protective insulating film being left on the logic circuit portion of the semiconductor substrate during the formation of the second well region in the logic circuit portion, the entrance of a contaminant into the semiconductor substrate due to an increased acceleration energy can be prevented.
In the method for fabricating a nonvolatile semiconductor device of the present invention, the third step preferably includes etching a region of the first insulating film contained in the logic circuit portion such that a lower portion thereof is left to cover the logic circuit portion and thereby forming a partial film composed of the first insulating film and the fourth step preferably includes forming the second well region by implanting ions into the logic circuit portion through the partial film and the protective insulating film. The arrangement more positively prevents a contaminant from entering the semiconductor substrate.
In the method for fabricating a nonvolatile semiconductor device of the present invention, the fourth step preferably includes selectively forming a third well region of a second conductivity type in the logic circuit portion of the semiconductor substrate. The arrangement allows the formation of a CMOS circuit in the logic circuit portion and prevents the third well region from experiencing the thermal budget resulting from the formation of the first insulating film and the first conductor film on the memory circuit portion.
Preferably, the method for fabricating a nonvolatile semiconductor device of the present invention further comprises, between the first and second steps, the step of: implanting impurity ions of a second conductivity type into the semiconductor substrate to form a fourth well region of the second conductivity type under the first well region. The arrangement provides the first well region composed of a multi-well structure, while using the mask pattern for forming the first well region without any alterations.
In the method for fabricating a nonvolatile semiconductor device of the present invention, the step of forming the fourth well region preferably includes implanting impurity ions of the first conductivity type and impurity ions of the second conductivity type and a projected range of the impurity ions of the second conductivity type is preferably larger than a projected range of the impurity ions of the first conductivity type.
Preferably, the method for fabricating a nonvolatile semiconductor device of the present invention further comprises, between the second and third steps, the step of: forming a third insulating film containing a nitride on the region of the first conductor film contained in the memory circuit portion, the third step includes performing the patterning so as to leave a region of the third insulating film contained in the memory circuit portion, wherein the fifth step includes forming the second insulating film on the third insulating film, and the sixth step includes forming the capacitance insulating film from the second and third insulating films. The arrangement provides the capacitance insulating film composed of a silicon oxynitride, preferably an ONO film, between the floating gate electrode and the control gate electrode.